Dot Matrix LED Scan
In general, MCU will leverages its timer interrupt service routine to drive its GPIO pins to do matrix LED scan for row & column matrix. This traditional approach will consumes a lot of MCU performance but unstable display quality when system is busy. This IP will generate necessary scan timing to drive row side and column side automatically. In other words, MCU takes no CPU cycle for display and just write desired data to a display RAM region. Scan area convers from 256x32 up to NxN.
As a ELD series with Avalon bus, this IP guarantees the higeset system performance, easy to integrate and results in the lowest system cost. Its density keeps less than 100 LEs. Amazing!
As a ELD series with Avalon bus, this IP guarantees the higeset system performance, easy to integrate and results in the lowest system cost. Its density keeps less than 100 LEs. Amazing!
6 Channels PWM Generator for Motor & Inverter Applications
This IP can offer 6 channels PWM outputs that synchronizes to the same start phase for output. The 6 PWM channels can drive 6 IGBT or Power MOS FET to 3 high sides and 3 low sides.
With Avalon MM bus, system can esay integrate this IP with Altera Qsys platform.
As a ELD series family IP, this IP also have itsd ensity of 100 LEs.
With Avalon MM bus, system can esay integrate this IP with Altera Qsys platform.
As a ELD series family IP, this IP also have itsd ensity of 100 LEs.
Extreme Low Density UART Controller
Extreme Low Density UART Controller is a Avalon MM based UART core. This core is fully verified by multiple projects. As a ELD series IP core, this core size is less than 100 LEs which is very suitable for system integration to maximum reduce system cost.
Extreme Low Density LPC Slave Controller
Extreme Low Density LPC Slave controller bridges Low Pin Count interface to Avalon MM slave for Altera Qsys system.
As a ELD series IP, this IP density is less than 100 LEs which is very suitable for system integration to maximum reduce system cost but also offer rich functions to connect to Intel based server platform.
As a ELD series IP, this IP density is less than 100 LEs which is very suitable for system integration to maximum reduce system cost but also offer rich functions to connect to Intel based server platform.
Avalon MM Cache Controller
Avalon MM Cache Controller is a customized cache controller for Avalon bus.
This IP can easy be integrated to Altera Qsys system to replace NIOS-II cache controller or as L2 cache controller. With embedded RAM and Flash memory controller, this IP can also connect to external SPI Flash for NIOS-II ELF code.
This IP can easy be integrated to Altera Qsys system to replace NIOS-II cache controller or as L2 cache controller. With embedded RAM and Flash memory controller, this IP can also connect to external SPI Flash for NIOS-II ELF code.
Extreme Low Density IIC host Controller
TPGE announced ELD series IP - IIC host controller. This IP can easy connect to Avalon MM slave bus and offer an IRQ for interrupt service routine. IP core density is less than 100 LEs. This IP is not for standalone license but will used to integrate with your whole system needs.
